When an internal circuit of a semiconductor device is tested, pads and/or external terminals for inputting signals which are required for testing the semiconductor device must be provided in the semiconductor device. However, when the number of the pads is increased, the chip area of the semiconductor device is increased, in addition, when the number of the external terminals is further increased, in some cases, the package of the semiconductor device must be large, and these greatly influence the cost and the size of a product including the semiconductor device. That is, the number of the pads and the number of the external terminals for the signals which are used for only testing the semiconductor device are desired to be as small as possible.
Therefore, when signals of an internal circuit not directly connected to the pads and the external terminals need to be tested, signals output from existing pads and terminals are obtained instead, and states of the signals of the internal circuit have been estimated.
For example, in a constant voltage circuit shown in FIG. 3, an operating mode is switched between a normal operating mode and an energy saving operating mode based on an output current Io.
As shown in FIG. 3, the constant voltage circuit provides a first error amplifying circuit 11 which is always operated and a second error amplifying circuit 12 which is operated at only the normal operating mode.
The first error amplifying circuit 11 is an amplifying circuit whose response speed is slow but consumption current is small, and the second error amplifying circuit 12 is an amplifying circuit whose response speed is fast but consumption current is great. Input terminals of the first and second error amplifying circuits 11 and 12 are connected to each other, and output terminals of the first and second error amplifying circuits 11 and 12 are connected to each other. In the first and second error amplifying circuits 11 and 12, a reference voltage Vref is applied to inverting input terminals, a voltage Vfb in which an output voltage Vo is divided by resistors R11 and R12 is applied to non-inverting input terminals, and the output terminals are connected to the gate of an output transistor M11.
The second error amplifying circuit 12 further provides a control input terminal. The second error amplifying circuit 12 provides a built-in switching circuit which switches its own operating mode, and the switching circuit controls the operating mode of the second error amplifying circuit 12 corresponding to a signal applied to the control input terminal.
An output from an OR circuit 13 is input to the control input terminal. When a signal input to the control input terminal is a low level, the second error amplifying circuit 12 stops operating, and the consumption current becomes substantially a 0 ampere. In addition, when a signal input to the control input terminal is a high level, the second error amplifying circuit 12 operates, and the consumption current becomes substantially a normal value.
A first input terminal of the OR circuit 13 is connected to a mode selection pad MODE and also connected to ground potential via a resistor R14. Therefore, when a signal is not applied to the mode selection pad MODE, the OR circuit 13 is in a low level. In addition, a second input terminal of the OR circuit 13 is connected to an output terminal of an inverter 15.
A switching signal generating circuit is formed of a PMOS transistor M12, a resistor R13, and inverters 14 and 15.
A current mirror circuit is formed of the PMOS transistor M12 and the output transistor M11. The output current Io is detected as a drain current Id12 of the PMOS transistor M12, and the resistor R13 connected between the drain of the PMOS transistor M12 and ground potential converts the drain current Id12 into a voltage.
When the converted voltage is less than a threshold voltage of the inverter 14, an output from the inverter 14 becomes a high level and an output from the inverter 15 becomes a low level, and an input to the second input terminal of the OR circuit 13 becomes a low level. When no signal is input to the mode selection pad MODE, a signal input to the first input terminal of the OR circuit 13 is the low level; therefore, an output from the OR circuit 13 is a low level, and a signal input to the control input terminal of the second error amplifying circuit 12 becomes a low level. Then, the second error amplifying circuit 12 stops operating and enters the energy saving operating mode.
When the converted voltage is the threshold voltage of the inverter 14 or more, the output from the inverter 15 becomes a high level, and a signal input to the control input terminal of the second error amplifying circuit 12 becomes a high level via the OR circuit 13; therefore, the second error amplifying circuit 12 is operated and enters the normal operating mode.
Since the voltage input to the inverter 14 is a hysteresis voltage, the threshold voltage when the energy saving operating mode is switched to the normal operating mode is determined to be higher than the threshold voltage when the normal operating mode is switched to the energy saving operating mode. With this, jitter at switching the operating modes is prevented.
In addition, in the constant voltage circuit, when a signal of a high level is input to the mode selection pad MODE, an output from the OR circuit 13 is always a high level; therefore, the second error amplifying circuit 12 enters the normal operating mode regardless of the output from the inverter 15.
The output current Io is shown in Equation (1) when the operating mode is switched by the switching signal generating circuit.Io=Vth/(K×R13)  (1)
Where, Vth is a threshold voltage of the inverter 14, “K” is a mirror ratio (Id12/Io) between the PMOS transistor M12 and the output transistor M11, and R13 is a resistance value of the resistor R13.
The values of the Vth, K, and R13 in Equation (1) are dispersed while the semiconductor device is manufactured, respectively; therefore, in order to accurately determine the value of the output current Io when the operating mode is switched, the resistance value R13 in Equation (1) is adjusted by trimming. Specifically, the output current Io is measured when the operating mode is switched while the output current Io is increased or decreased, and the trimming amount of the resistor R13 is calculated from the measured output current Io.
However, an output from the inverter 15 which outputs an internal switching signal for switching the operating mode is not connected to a pad and/or an external terminal. Therefore, in order to obtain whether the operating mode is switched, a slight increase of a consumption current of a semiconductor device is detected by the operations of the second error amplifying circuit 12. However, the increase of the consumption current is a very small amount of the total consumption current; therefore, it is difficult to measure the output current Io when the operating mode is switched, and a high-cost testing instrument whose accuracy is high is required.
When a pad and/or an external terminal for only obtaining an internal switching signal output from the inverter 15 is provided, since the switching of the operating mode can be extracted as a logic level signal and can be tested, the output current Io at switching the operating mode can be accurately measured with the use of a low-cost instrument. However, as described above, since the internal switching signal is used only during the test, the pad and/or the external terminal for only the test undesirably influences the cost and the size of the product.
In order to solve the above problem, conventionally, a decrease of the number of testing terminals has been tried. For example, in a method of Patent Document 1, a signal of an internal circuit of a semiconductor device is output to a pad to which an output of a first circuit is connected, and an output from a second circuit whose output is to be tested is connected to the pad via a fuse. During the test of the second circuit, the output from the first circuit is made to be high impedance, and when the test of the second circuit is completed, the fuse is cut off.    [Patent Document 1] Japanese Unexamined Patent Publication No. 2006-313797
However, in patent Document 1, only when the first circuit and the second circuit are not operated at the same time and the output from the first circuit can be made to be the high impedance during the operation of the second circuit, the method can be operated.